Voltage converter with auto-isolation function

ABSTRACT

The disclosure relates to a voltage converter, converting a first signal of a first voltage to output a second signal of a second voltage. A level shifter receives the first signal to generate the second signal. An isolation circuit is coupled to the output of the level shifter, passing the second signal out. When the input of voltage converter is floated, the isolation circuit stops passing the second signal as the output, instead, the isolation circuit outputs a substitution signal having a predetermined voltage level irrelevant to the input of the level shifter.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.60/805,480, filed 2006, Jun. 22.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a system on chip (SOC), and more particularly,to isolation circuits in a level shifter.

2. Description of the Related Art

FIG. 1 shows a conventional system on chip (SOC) utilizing a levelshifter 100. Signals passed between the first voltage domain 110 and thesecond voltage domain 120 are converted by the level shifter 100 toadapt to the corresponding voltage domain. There are various knowntechniques for implementing level shifter 100, thus, a detaileddescription thereof is omitted. In an SOC, however, the first voltagedomain 110 or second voltage domain 120 may be selectively oroccasionally powered down, switching the corresponding terminal on levelshifter 100 to a floating state. For example, when the first terminal V1is floated, the level shifter 100 may output an indeterminable signal tothe second terminal V2. If the second voltage domain 120 receives theindeterminable signal, unexpected application errors may occur.

BRIEF SUMMARY OF THE INVENTION

Voltage converters are provided. An exemplary embodiment of a voltageconverter converts a first signal of a first voltage to output a secondsignal of a second voltage. A level shifter receives the first signal togenerate the second signal. An isolation circuit is coupled to theoutput of the level shifter for outputting the second signal. When theinput of voltage converter is floated, the isolation circuit stopsoutput of the second signal, instead, the isolation circuit outputs asubstitution signal having a predetermined voltage level irrelevant tothe input of the level shifter.

Another embodiment of the voltage converter is bi-directional,converting the first signal of a first voltage to and from a secondsignal of a second voltage. A level shifter comprising a first terminaland a second terminal, receives the first signal from the first terminalto generate the second signal on the second terminal, or conversely,receives the second signal from the second terminal to generate thefirst signal on the first terminal. A first isolation circuit is coupledto the second terminal of level shifter, passing the second signaloutbound the voltage converter. When the first terminal is floated, thefirst isolation circuit stops passing the second signal, instead, thefirst isolation circuit outputs a substitution signal irrelevant to theinput on the first terminal. A second isolation circuit is coupled tothe first terminal of level shifter, passing the first signal outboundfrom the voltage converter. When the second terminal is floated, thesecond isolation circuit stops passing the first signal, instead, thesecond isolation circuit outputs a substitution signal irrelevant to theinput on the second terminal.

The first isolation circuit may be a latch circuit that latches thelatest status of the second signal when the first terminal is floated,or a pulling circuit that pulls the second signal to a predeterminedvoltage level when the first terminal is floated. The second isolationcircuit is also a latch circuit or a pulling circuit. A detaileddescription is given in the following embodiments with reference to theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the subsequentdetailed description and examples with references made to theaccompanying drawings, wherein:

FIG. 1 shows a conventional system on chip (SOC) utilizing a levelshifter 100;

FIG. 2 shows an embodiment of SOC utilizing voltage conversion unitswith signal isolation;

FIGS. 3 a and 3 b show embodiments of auto-latch circuits in the voltageconverter 200 a;

FIGS. 4 a to 4 f show embodiments of pulling circuits coupled to theoutput terminal of level shifter 100; and

FIGS. 5 a to 5 f show embodiments of pulling circuits coupled to thecomplementary output terminal of level shifter 100.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated mode of carryingout the invention. This description is made for the purpose ofillustrating the general principles of the invention and should not betaken in a limiting sense. The scope of the invention is best determinedby reference to the appended claims.

FIG. 2 shows an embodiment of SOC utilizing voltage conversion unitswith automatic signal isolation. In FIG. 2, the voltage converter 200 ahas two terminals, a first terminal V1 and a second terminal V2individually connected to the first voltage domain 110 and the secondvoltage domain 120. The voltage domain of signals sent from the firstvoltage domain 110 is converted to the voltage domain of the secondvoltage domain 120. The voltage converter 200 a comprises a levelshifter 100 and an isolation circuit 202. The isolation circuit 202 iscoupled to the output of level shifter 100 and the input of secondvoltage domain 120. When the first voltage domain 110 operates normally,a signal sent to the first terminal V1 is converted and passed to thesecond terminal V2 bound for the second voltage domain 120. When thefirst voltage domain 110 powers down, the first terminal V1 is floated.In response, the isolation circuit 202 stops passing the convertedsignal to second terminal V2, and instead, the isolation circuit 202outputs a substitution signal having a predetermined voltage levelirrelevant to the input of the first terminal V1. The isolation circuit202 automatically isolates an undetermined voltage level of the outputof the level shifter 100, and the isolation circuit 202 provides asubstitution signal at the output of the level shifter 100. The term“automatically isolate” means that an isolation circuit does not need acontrol input. The isolation circuit only needs to be coupled to avoltage source and coupled to an output of a level shifter.

FIGS. 3 a and 3 b show embodiments of auto-latch circuits in the voltageconverter 200 a. In FIG. 3 a, a typical level shifter 300 a comprisestransistors M1, M2, M3, and M4, and inverters 102, 104 and 106. Signalsfrom the first terminal V1 are input to the transistor pairs M3 and M4,and the inverters 104 and 106 are serially coupled to the outputterminal B for outputting converted signals. The isolation circuit 202is implemented by an inverter 310 coupled to the inverter 104 inreverse, feeding the output of inverter 104 back to the input of theinverter 310. The inverter 310 and inverter 104 jointly form a latchcircuit capable of latching the voltage at the node C. The inverter 310is intentionally designed to be weaker than level shifter 300 a, thus,when the input of level shifter 300 a does not float, the outputterminal is dominated by the level shifter 300 a to output convertedsignals via the inverters 104 and 106. When the input of level shifter300 a is floated, voltage at the first terminal V1 becomesindeterminable, thus, the latch circuit formed by the inverters 310 and104 turns out to be effective, preserving the latest status on node Cand outputting it as a substitution signal. It is noted that throughoutthe detailed description, the level shifter 300 a is used as an example.There are various types of level shifters known by persons skilled inthe art. These various types of level shifters can be chosen by acircuit designer to implement an embodiment of the invention.

FIG. 3 b shows a similar case using the complementary output terminal oflevel shifter 300 b. In a conventional solution a first inverter 108 iscoupled to the complementary output terminal A for output of a convertedsignal. An inverter 310 is added to form a latch circuit with the firstinverter 108. Normally, the first inverter 108 outputs a convertedsignal to the second terminal V2 while the latching effect of inverter310 is weaker. When voltage at the first terminal V1 becomes unstable,signals maintained by the inverter 310 override signals generated by thetransistors M1 and M3, and the latest status on the second terminal V2is latched and output as a substitution signal.

FIGS. 4 a to 4 f show embodiments of pulling circuits coupled to theoutput terminal of level shifter 400 a. In FIG. 4 a, the isolationcircuit 202 is implemented as a pulling circuit 410, coupled to thesupply voltage VCC and output terminal B, and is weaker than transistorsM2 and M4. Normally, when the input of level shifter 400 a is notfloating, the voltage at the output terminal B is dominated by the M2and M4 to output the converted signal. Conversely, when the input oflevel shifter 400 a is floated, the pulling circuit 410 begins todominate the voltage at the output terminal B, such that thesubstitution signal is output to the second terminal V2.

FIG. 4 b shows an embodiment of the pulling circuit 410 implemented by aPMOS in which, the gate is grounded, and the source and drain areindividually coupled to supply voltage VCC and the output terminal B.This arrangement tends to constantly pull the voltage at the outputterminal B to the supply voltage VCC. To make the POMS weaker, the PMOSis implemented by a long channel device, such that when in normaloperation, the voltage at the output terminal B is dominated by thetransistors M2 and M4. When the input of level shifter 400 a is floated,the voltage at the output terminal B is pulled to supply voltage VCC bythe pulling circuit 410.

FIG. 4 c shows an embodiment of the pulling circuit 410 implemented by acapacitor, with two terminals thereof coupled to the output terminal Band the supply voltage VCC. When the input of the level shifter 400 a isfloating, the transistor M2 and M4 are too weak to control the outputterminal B with a strong driving capability. Subsequently, the outputterminal B is charged (through M2) to a voltage level near VCC. Thus,the output terminal B is at a high state (logic 1). In this situation,the capacitor C has an effect to keep the output terminal B high and thevoltage level of the terminal B is irrelevant to the floating input ofthe level shifter 400 a. To make the capacitor weaker, the capacitor isdesigned to be small, such that when in normal operation, voltage at theoutput terminal B is dominated by transistors M2 and M4. When the inputof level shifter 400 a is floated, the voltage at the output terminal Bis pulled to the supply voltage VCC by the pulling circuit 410.

In FIG. 4 d, the isolation circuit 202 is implemented as a pullingcircuit 420, coupled between the ground and the output terminal B. Theisolation circuit is weaker than level shifter 400 b. The pullingcircuit 420 tends to constantly pull the voltage at the output terminalB to ground. Typically, when the input of level shifter 400 b is notfloating the voltage at the output terminal B is dominated by thetransistors M2 and M4 and the converted signal is output. Conversely,when the input of level shifter 400 b is floated, the pulling circuit420 begins to dominate the voltage at the output terminal B, such thatthe ground voltage is output to the second terminal V2 as thesubstitution signal.

FIG. 4 e shows an embodiment of the pulling circuit 420 implemented by aNMOS in which, the gate is coupled to the supply voltage VCC, and thesource and drain are individually coupled to ground and the outputterminal B. This arrangement tends to constantly pull the voltage atoutput terminal B to ground. To make the NMOS weaker, the NMOS isimplemented by a long channel device such that when in normal operation,voltage at the output terminal B is dominated by transistors M2 and M4.When the input of level shifter 400 b is floated, the voltage at theoutput terminal B is pulled to ground by the pulling circuit 420.

FIG. 4 f shows another embodiment of the pulling circuit 420 implementedby a capacitor, with two terminals thereof coupled to the outputterminal B and ground. When the input of the level shifter 400 b isfloating, the transistor M2 and M4 are too weak to control the outputterminal B with a strong driving capability. Subsequently, the outputterminal B is discharged (through M4) to a voltage level near GND(ground). Thus, the output terminal B is at a low state (logic 0). Inthis situation, the capacitor C has an effect to keep the outputterminal B low and the voltage level of the terminal B is irrelevant tothe floating input of the level shifter 400 b. To make the capacitorweaker, the capacitor is designed to be small, such that when in normaloperation, voltage at the output terminal B is dominated by transistorsM2 and M4. When the input of level shifter 400 b is floated, the voltageat the output terminal B is pulled to ground by the pulling circuit 420.The pulling circuits 410 and 420 are not limited to be the describedcapacitor or NMOS/PMOS, however, they can be any circuit capable ofpulling the voltage to a predetermined level irrelevant to voltage atthe first terminal V1.

FIGS. 5 a to 5 f show embodiments of pulling circuits coupled to thecomplementary output terminal A of the level shifter 500 a. Sincevoltage at the complementary output terminal A is an inversion of theinput at first terminal V1, a first inverter 108 is coupled to thecomplementary output terminal A to reverse the voltage and output aconverted signal at the second terminal V2. The pulling circuit 510 isdesigned to be weak, tending to pull the voltage at the complementaryoutput terminal A to a predetermined level. Similar to the embodimentdescribed in FIG. 4 a, when the input of level shifter 500 a is notfloated, the voltage at the complementary output terminal A is dominatedby the transistors M1 and M3 to output a converted signal via the firstinverter 108. When the input of level shifter 500 a is floated, thevoltage at the complementary output terminal A is dominated by thepulling circuit 510 to output a substitution signal via the firstinverter 108.

FIG. 5 b shows an embodiment of the pulling circuit 510 implemented by aPMOS. In which, the gate is grounded, and the source and drain areindividually coupled to supply voltage VCC and the complementary outputterminal A. This arrangement tends to constantly pull the voltage at thecomplementary output terminal A to supply voltage VCC. To make the PMOSweaker, the PMOS is implemented by a long channel device, such that whenin normal operation, voltage at the complementary output terminal A isdominated by M1 and M3. When the input of level shifter 500 a isfloated, the voltage at the complementary output terminal A is pulled tosupply voltage VCC by the pulling circuit 510. Through the firstinverter 108, a ground signal is output to second terminal V2 as asubstitution signal.

FIG. 5 c shows an embodiment of the pulling circuit 510 implemented by acapacitor, with two terminals thereof coupled to the complementaryoutput terminal A and the supply voltage VCC. When the input of thelevel shifter 500 a is floating, the transistor M1 and M3 are too weakto control the output terminal A with a strong driving capability.Subsequently, the output terminal A is charged (through M1) to a voltagelevel near VCC. Thus, the output terminal A is at a high state (logic1). In this situation, the capacitor C has an effect to keep the outputterminal A high and the voltage level of the terminal A is irrelevant tothe floating input of the level shifter 500 a. To make the capacitorweaker, the capacitor is designed to be small, such that when in normaloperation, voltage at the complementary output terminal A is dominatedby transistors M1 and M3. When the input of level shifter 500 a isfloated, the voltage at the complementary output terminal A is pulled tosupply voltage VCC by the pulling circuit 510. Similarly, a groundsignal is output to the second terminal V2 as a substitution signalthrough the first inverter 108.

In FIG. 5 d, the isolation circuit 202 is implemented as a pullingcircuit 520 coupled between the ground and complementary output terminalA, weaker than level shifter 500 b. The pulling circuit 520 tends toconstantly pull the voltage at the complementary output terminal A toground. Normally, when the input of level shifter 500 b is not floated,the voltage at the complementary output terminal A is dominated by thetransistors M1 and M3 to output the converted signal. Conversely, whenthe input of level shifter 500 b is floated, the pulling circuit 510begins to dominate the voltage at the complementary output terminal A,such that the voltage at the complementary output terminal A is pulledto ground. Through the first inverter 108, a high voltage is output tothe second terminal V2 as a substitution signal.

FIG. 5 e shows an embodiment of the pulling circuit 520 implemented by aNMOS. In which, the gate is coupled to the supply voltage VCC, and thesource and drain are individually coupled to ground and thecomplementary output terminal A. This arrangement tends to constantlypull the voltage at the complementary output terminal A to ground. Tomake the NMOS weaker, the NMOS is implemented by a long channel device,such that when in normal operation, voltage at the complementary outputterminal A is dominated by transistors M1 and M3. When the input oflevel shifter 500 b is floated, the voltage at the complementary outputterminal A is pulled to ground by the pulling circuit 520.

FIG. 5 f shows another embodiment of the pulling circuit 520 implementedby a capacitor, with two terminals thereof coupled to the complementaryoutput terminal A and ground. When the input of the level shifter 500 bis floating, the transistor M1 and M3 are too weak to control the outputterminal A with a strong driving capability. Subsequently, the outputterminal A is discharged (through M3) to a voltage level near GND(ground). Thus, the output terminal A is at a low state (logic 0). Inthis situation, the capacitor C has an effect to keep the outputterminal A low and the voltage level of the terminal A is irrelevant tothe floating input of the level shifter 500 b. To make the capacitorweaker, the capacitor is designed to be small, such that when in normaloperation, voltage at the complementary output terminal A is dominatedby transistors M1 and M3. When the input of level shifter 500 b isfloated, the voltage at the complementary output terminal A is pulled toground by the pulling circuit 520. The pulling circuits 510 and 520 arenot limited to be the described capacitor or NMOS/PMOS, to the contrary,they can be any circuit capable of pulling the voltage to apredetermined level irrelevant to the input at the first terminal V1.

The level shifters in the embodiments can be uni-directional orbi-directional, and the implementation thereof is not limited to thedescribed embodiments. The second isolation circuit 204 can be identicalto the isolation circuit 202, thus, redundant descriptions are omitted.With the auto-isolation function implemented in the level shifters, aSOC achieves higher quality and performance with lower cost.

While the invention has been described by way of example and in terms ofpreferred embodiment, it is to be understood that the invention is notlimited thereto. To the contrary, it is intended to cover variousmodifications and similar arrangements (as would be apparent to thoseskilled in the art). Therefore, the scope of the appended claims shouldbe accorded the broadest interpretation so as to encompass all suchmodifications and similar arrangements.

1-14. (canceled)
 15. A voltage converter for converting a first signalof a first voltage into a second signal of a second voltage, comprising:a level shifter, further comprising: an input terminal, for inputtingthe first signal; an output terminal, for outputting the second signal;and a first inverter, comprising: an output; and an input, coupled tothe output terminal; and an isolation circuit, for feeding the output ofthe first inverter back to the input of the first inverter; wherein: thelevel shifter dominates the output terminal of the level shifter tooutput the second signal via the first inverter when the input terminalof the level shifter is not floating; and the isolation circuitintegrates the first inverter of the level shifter to form a latchcircuit to continue outputting a previous state of the second signal asa substitution signal of the second signal when the input terminal oflevel shifter is floating.
 16. A voltage converter as claimed in claim15, wherein the isolation circuit comprises an inverter, wherein theinverter comprises an input end coupled to the output of the firstinverter of the level shifter and an output end coupled to the input ofthe first inverter of the level shifter.
 17. A voltage converter forconverting a first signal of a first voltage into a second signal of asecond voltage, comprising: a level shifter, for outputting the secondsignal when an input terminal of the level shifter is not floating; anda latch circuit, coupled to an output terminal of the level shifter, forautomatically outputting a previous state of the second signal as asubstitution signal of the second signal when the input terminal oflevel shifter is floating.
 18. A voltage converter as claimed in claim17, wherein the latch circuit comprises: an first inverter, furthercomprising: a first input, coupled to the output terminal of the levelshifter; and a first output; and an second inverter, further comprising:a second input, coupled to the first output of the first inverter; and asecond output, coupled to the first input of the first inverter.